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32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
Integrated Device Technology, Inc.
IDT49C465 IDT49C465A
FEATURES
* * * * * * * * * * * * * *
32-bit wide Flow-thruEDCTM unit, cascadable to 64 bits Single-chip 64-bit Generate Mode Separate system and memory buses On-chip pipeline latch with external control Supports bidirectional and common I/O memories Corrects all single-bit errors Detects all double-bit errors, some multiple-bit errors Error Detection Time -- 12ns Error Correction Time -- 14ns On chip diagnostic registers. Parity generation and checking on system data bus Low power CMOS -- 100mA typical at 20MHZ 144-pin PGA and PQFP packages Military product compliant to MIL-STD 883, Class B
DESCRIPTION
The IDT49C465/A is a 32-bit, two-data bus, Flow-thruEDC unit. The chip provides single-error correction and two and three bit error detection of both hard and soft memory errors. It can be expanded to 64-bit widths by cascading 2 units, without the need for additional external logic. The FlowthruEDC has been optimized for speed and simplicity of control. The EDC unit has been designed to be used in either of two configurations in an error correcting memory system. The bidirectional configuration is most appropriate for systems using bidirectional memory buses. A second system configuration utilizes external octal buffers, and is well suited for systems using memory with separate I/O buses. The IDT49C465/A supports partial word writes, pipelining and error diagnostics. It also provides parity protection for data on the system side.
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
MD0-31 Correct Logic Memory Checkbit Generator
MD Latch
MLE Checkbit Latch
Syndrome Generator
Expansion Logic
ERR Detect Logic MERR
CBI0-7
Mux
PCBI0-7 SD0-31
Pipeline Latch
CONTROL CONTROL Byte Mux System Checkbit Generator
SD Latch SLE PLE
Mux
CBO0-7
2552 drw 01
CONTROL
CONTROL
The IDT logo is a registered trademark and Flow-thruEDC is a trademarkof Integrated Device Technology Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1995 Integrated Device Technology, Inc.
AUGUST 1995
DSC-9028/7
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IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
SD2 SD1 SD0 PCBI7 PCBI6 PCBI5 PCBI4 PCBI3 PCBI2 PCBI1 PCBI0 CODE ID 1 CODE ID 0 GND GND MODE 1 MODE 0
VCC SD5 SD6 SD7 SD8 SD9 SD10 SD11 GND BE1 SD12 SD13 SD14 SD15 SLE PLE SOE GND SD16 SD17 SD18 SD19 BE2 SD20 SD21 SD22 GND SD23 SD24 SD25 SD26 SD27 BE3 SD28 VCC VCC
72 73
MERR ERR SYO7 SYO6 SY05 SY04 GND SY03 SYO2 SYO1 SYO0 MD0 MD1 MD2 VCC
VCC
SD4 BE0
SD3
37 36
49C465Y PQ144-2
108 109
SD29 SD30 SD31 CBO0 CBO1 CBO2 CBO3 CBOE CBO4 CBO5 CBO6 CBO7 PSEL PERR P3 P2 GND GND P1 P0 MODE 2 VCC
1 144
SYNCLK SCLKEN CLEAR CBI0 CBI1 CBI2 CBI3 GND CBI4 CBI5 CBI6 CBI7 MD31 VCC
VCC VCC MD3 MD4 MD5 MD6 MD7 MD8 MD9 GND MD10 MD11 MD12 MD13 MD14 MD15 MLE MOE GND MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 GND MD24 MD25 MD26 MD27 MD28 MD29 MD30 VCC
2552 drw 02
PQFP TOP VIEW
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IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
VCC
CODE CODE MODE SD 2 PCBI 6 PCBI 5 PCBI 3 ID 1 MERR ERR SYO 5 SYO 3 SYO 1 MD 1 1 ID 0 SD 1 PCBI 7 PCBI 4 PCBI 1 PCBI 0 MODE SYO 6 SYO 4 SYO 2 MD 0 MD 2
0
VCC MD 5
SD 6 SD 4 SD 9 SD 5
VCC
BE 0 VCC
SD 3
SD 0 PCBI 2 GND
GND SYO 7 GND SYO 0 VCC
MD 3 MD 4
MD 6 MD 9 MD 8 GND
SD 11 SD 7
SD 12 SD 10 SD 8 SD 15 SLE SOE BE 1 GND
MD 7 MD 10 MD 11 MD 12 MD 13 MD 15 MOE MD 14 MLE G144-2 GND MD 17 MD 16 MD 20 MD 21 MD 18 GND MD 23 MD 19 MD 27 MD 25 MD 22 NC* VCC CB0 0 CBOE CB0 7 GND GND P3 P2 H VCC MD 28 MD 24
SD 13 SD 14 PLE GND
SD 17 SD 19 SD 16 SD 18 BE 2 SD 20
SD 21 SD 22 SD 25 GND SD 24 BE 3
SD 23 SD 26 SD 28 SD 27 VCC A
VCC SD 29 SD 31 CB0 2 CB0 4 CB0 6 SD 30 CB0 1 CB0 3 CB0 5 PSEL PERR B C D E F G
SCLK GND CB1 6 CB1 7 MD 30 MD 26 EN MODE SYN2 CLK CB1 0 CB1 3 CB1 4 MD 31 MD 29 P1 J P0 K
CLEAR CB1 1 CB1 2 CB1 5 VCC
L
M
N
P
R
2552 drw 03
*Tied to Vcc internally
PGA (CAVITY UP) TOP VIEW
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Dashed Line = Diagnostic path ERROR DETECT
8 8 8 8 8
ERR MERR PCBI 0-7
MUX
8
INTERNAL FINAL SYNDRO ME MUX CHECK BIT LATCH
8
SYNDROME GENERATOR MUX
8 8
8
SYO0-7 MUX
CBI0-7
PLE
8
MD CHECKBIT GENERATOR MD LATCH
MLE
SOE ERROR CORRECT MUX PIPE LATCH DIAGNOSTIC LATCHES ERROR DATA LATCH
BE0-3
4
1 OF 4 BYTES
CLEAR MD0-31 INTERNAL SYNCLK BYTE MUX
IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
DETAILED FUNCTIONAL BLOCK DIAGRAM
SD0-31 SD LATCH BE 0-3
4
11.7
8
MOE
SLE
PSEL
4
MUX
P0-3
4
PARITY GEN
SD CHECKBIT GENERATOR
8
8
CBO0-7 CBOE
8
4
PARITY CHECK
MUX
PERR
SD CHECKBIT GENERATOR
/ERR
INTERNAL SYNCLK
8
PCBI0-7
SYNCLK SCLKEN CLEAR
2
CODE ID 0,1 MODE0-2
3
CONTROL LOGIC
2552 drw 04
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IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
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SYSTEM CONFIGURATIONS
The IDT49C465 EDC unit can be used in various configurations in an EDC system. The basic configurations are shown below. Figure 1 illustrates a bidirectional configuration, which is most appropriate for systems using bidirectional memory buses. It is the simplest configuration to understand and use. During a correction cycle, the corrected data word can be simultaneously output on both the system bus and memory bus. Logically, no other parts are required for the correction function. During partial-word-write operations, the new bytes are internally combined with the corrected old bytes for checkbit generation and writing to memory.
Figure 3 illustrates a third configuration which utilizes external buffers and is also well suited for systems using memory with separate I/O buses. Since data from memory does not need to pass through the part on every cycle, the EDC system may operate in "bus-watch" mode. As in the separate I/O configuration, corrected data is output on the SD outputs.
MEMORY INPUT BUS CHECKBIT I/O MEMORY OUTPUT BUS
CBO SD EDC
CBI MD
CPU I/O
SD EDC
MD
MEMORY I/O
EXT. BUFFER EXT.BUFFER EXT. BUFFER CPU BUS
2552 drw 07
CBI CHECKBITS CBO
2552 drw 05
Figure 1. Common I/O Configuration
Figure 3. Bypassed Separate I/O Configuration
Figure 2 illustrates a separate I/O configuration. This is appropriate for systems using separate I/O memory buses. This configuration allows separate input and output memory buses to be used. Corrected data is output on the SD outputs for the system and for re-write to memory. Partial word-write bytes are combined externally for writing and checkbit generation.
CPU
Figure 4 illustrates the single-chip generate-only mode for very fast 64-bit checkbit generation in systems that use separate checkbit-generate and detect-correct units. If this is not desired, 64-bit checkbit generation and correction can be done with just 2 EDC units. 64-bit correction is also straightforward, fast and requires no extra hardware for the expansion.
CHECK BITS OUT
CHECK BITS IN MEMORY INPUT BUS
EXT. BUFFER
MEMORY INPUTS
MEMORY OUTPUT BUS
MEMORY INPUT BUS CBO 64-BIT GEN. ONLY
CBI LOWER DATA EDC BUFFER BUFFER UPPER DATA EDC BUFFER
SD MD EDC CBI CHECKBITS CBO
2552 drw 06
MEMORY OUTPUTS
BUFFER
EDC
CPU BUS
2552 drw 08
Figure 2. Separate I/O Configuration
Figure 4. Separate Generate/Correction Units with 64-Bit Checkbit Generation
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FUNCTIONAL DESCRIPTION
The error detection/correction codes consist of a modified Hamming code; it is identical to that used in the IDT49C460. 32-BIT MODE (CODE ID 1,0=00)
VCC 8 PCBI CBI7 CHECKBITS-IN 7 CBI0-6 SYO 7 SYNDROME-OUT CBO 7 CHECKBITS-OUT
EDC
Figure 5. 32-Bit Mode
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64-BIT MODE (CODE ID 1,0=10 & 11) The expansion bus topology is shown in Figure 6. This topology allows the syndrome bits used by the correction logic to be generated simultaneously in both parts used in the expansion. During a 64-bit detection or correction operation,
"Partial-Checkbit" data and "Partial-Syndrome" data is simultaneously exchanged between the two EDC units in opposite directions on dedicated expansion buses. This results in very short 64-bit detection and correction times.
8 PARTIAL-CHECKBITS-OUT (11) (CORRECTION ONLY) PCBI CBO 8 PARTIAL-CHECKBITS-OUT (10) (GENERATE ONLY) 8 PARTIAL-SYNDROME (DETECT/CORRECT ONLY) PCBI CBO 8 FINAL CHECKBITS-OUT
CHECKBITS-IN
8
CBI
SYO
CBI
SYO
LOWER EDC (CODE ID 1,0 = 10)
ERR UPPER EDC (CODE ID 1,0 = 11)
(DETECT AND CORRECT)
2552 drw 10
Figure 6. 64-Bit Mode -- 2 Cascaded IDT49C465 Devices
64-BIT GENERATE-ONLY MODE (CODE ID 1,0=01) If the Identity pins CODE ID 1,0 = 01, a single EDC is placed in the 64-bit "Generate-only" mode. In this mode, the lower 32 bits of the 64-bit data word enter the device on the MD0-31 inputs and the upper 32-bits of the 64 bit data word enter the
device on the SD0-31 inputs. This provides the device with the full 64-bit word from memory. The resultant generated checkbits are output on the CBO0-7 outputs. The generate time is less than that resulting from using a 2-chip cascade.
LOWER 32 BITS (0-31) 32 UPPER 32 BITS (32-63) 32
MD0-31
CBO 8 CHECKBITS-OUT
SD0-31
EDC
2552 drw 11
Figure 7. 64-Bit "Generate-Only" Mode (Single Chip) 11.7 6
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PIN DESCRIPTIONS
Symbol SD0-7 SD8-15 SD16-23 SD24-31 I/O I/O Name and Function System Data Bus: Data from MD0-31 appears at these pins corrected if MODE 2-0 = x11, or uncorrected in the other modes. The BEn inputs must be high and the SOE pin must be low to enable the SD output buffers during a read cycle. (Also, see diagnostic section.) Separate I/O memory systems: In a write or partial-write cycle, the byte not-to-be-modified is output on SDn to n+7 for re-writing to memory, if BEn is high and SOE is low. The new bytes to be written to memory are input on the SDn pins, for writing checkbits to memory, if BEn is low. Bi-directional memory systems: In a write or partial-write cycle, the byte not-to-be-modified is re-directed to the MD I/O pins, if BEn is high, for checkbit generation and rewriting to memory via the MD I/O pins. SOE must be high to avoid enabling the output drivers to the system bus in this mode. The new bytes to be written are input on the SDn pins for checkbit generation and writing to memory. BEn must be low to direct input data from the System Data bus to the MD I/O pins for checkbit generation and writing to the checkbit memory. System Latch Enable: SLE is an input used to latch data at the SD inputs. The latch is transparent when SLE is high; the data is latched when SLE is low. Pipeline Latch Enable: PLE is an input which controls a pipeline latch, which controls data to be output on the SD bus and the MD bus during byte merges. Use of this latch is optional. The latch is transparent when PLE is low; the data is latched when PLE is high. System Output Enable: When low, enables System output drivers and Parity output drivers if corresponding Byte Enable inputs are high. Byte Enables: In systems using separate I/O memory buses, BEn is used to enable the SD and Parity outputs for byte n. The BEn pins also control the "Byte mux". When BEn is high, the corrected or uncorrected data from the Memory Data latch is directed to the MD I/O pins and used for checkbit generation for byte n. This is used in partial-word-write operations or during correction cycles. When BEn is low, the data from the System Data latch is directed to the MD I/O pins and used for checkbit generation for byte n. BE0 controls SD0-7 BE2 controls SD16-23 BE1 controls SD8-15 BE3 controls SD24-31 Memory Data Bus: These I/O pins accept a 32-bit data word from main memory for error detection and/ or correction. They also output corrected old data or new data to be written to main memory when the EDC unit is used in a bi-directional configuration. Memory Latch Enable: MLE is used to latch data from the MD inputs and checkbits from the CBI inputs. The latch is transparent when MLE is high; data is latched when MLE is low. When identified as the upper slice in a 64-bit cascade, the checkbit latch is bypassed. Memory Output Enable: I/O Buses and Controls
SLE
I I
PLE SOE
BE0-3
I I
MD0-31
I/O
MLE
I
MOE
P0-3
I I/O
MOE enables Memory Data Bus output drivers when low.
Parity I/O: The parity I/O pins for Bytes 0 to 3. These pins output the parity of their respective bytes when that byte is being output on the SD bus. These pins also serve as parity inputs and are used in generating the Parity ERRor (PERR) signal under certain conditions (see Byte Enable definition). The parity is odd or even depending on the state of the Parity SELect pin (PSEL). Parity SELect: If the Parity SELect pin is low, the parity is even. If the Parity SELect pin is high, the parity is odd.
PSEL Inputs CBI0-7
I
I
CheckBits-In (00) CheckBits-In-1 (10) Partial-Syndrome-In (11): In a single EDC system or in the lower slice of a cascaded EDC system, these inputs accept the checkbits from the checkbit memory. In the upper slice in a cascaded EDC system, these inputs accept the "PartialSyndrome" from the lower slice (Detect/Correct path). Partial-CheckBits-In (10) Partial-CheckBits-In (11): In a single EDC system, these inputs are unused but should not be allowed to float. In a cascaded EDC system, the "Partial-Checkbits" used by the lower slice are accepted by these inputs (Correction path only). In the upper slice of a cascaded EDC system, "Partial-Checkbits" generated by the lower slice are accepted by these inputs (Generate path). CODE IDentity: Inputs which identify the slice position/ functional mode of the IDT49C465. (00) Single 32-bit EDC unit (10) Lower slice of a 64-bit cascade (01) 64-bit "Checkbit-generate-only" unit (11) Upper slice of a 64-bit cascade
2552 tbl 01
PCBI 0-7
I
CODE ID1,0
I
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IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
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PIN DESCRIPTIONS (Con't.)
Symbol I/O Name and Function Inputs (Con't.) MODE 2-0 I (x11) (x10) (000) MODE select: Selects one of four operating modes. "Normal" Mode: Normal EDC operation (Flow-thru correction and generation). "Generate-Detect" Mode: In this mode, error correction is disabled. Error generation and detection are normal. "Error-Data-Output" Mode: Allows the uncorrected data captured from an error event by the Error-Data Register to be read by the system for diagnostic purposes. The Error-Data Register is cleared by toggling CLEAR low. The Syndrome Register and Error-Data Register record the syndrome and uncorrected data from the first error that occurs after they are reset by the CLEAR pin. The Syndrome Register and Error-Data Register are updated when there is a positive edge on SYNCLK, an error condition is indicated (ERR = low), and the Error Counter indicates zero. All-Zero-Data Source: In Error-Data-Output Mode, clearing the Error-Data Register provides a source of all-zero-data for hardware initialization of memory, if this desired. Diagnostic-Output Mode: In this mode, the contents of the Syndrome Register , Error Counter and ErrorType Register are output on the SD bus. This allows the syndrome bytes for an indicated error to be read by the system for error-logging purposes. The Syndrome Register and the Error-Data Register are updated when there is a positive edge on SYNCLK, an error condition is indicated and the Error Counter indicates zero errors. Thus, the Syndrome Register saves the syndrome that was present when the first error occurred after the Error Counter was cleared. The Syndrome Register and the Error Counter are cleared by toggling CLEAR low. The Error Counter lets the system tell if more than one error has occurred since the last time the Syndrome Register or Error-Data Register was read. Checkbit-Injection Mode: In the "Checkbit-Injection" Mode, diagnostic checkbits may be input on System Data Bus bits 0-7 (see Diagnostic Features - Detailed Description). CLEAR: When the CLEAR pin is taken low, the Error-Data Register, the Syndrome Register, the Error Counter and the Error-Type Register are cleared. SYNdrome CLocK: If ERR is low, and the Error Counter indicates zero errors, syndrome bits are clocked into the Syndrome Register and data from the outputs of the Memory Data input latch are clocked into the Error-Data Register on the low-to-high edge of SYNCLK. If ERR is low, the Error Counter will increment on the low-to-high edge of SYNCLK, unless the Error Counter indicates fifteen errors. SynCLK ENable: The SCLKEN enables the SYNCLK signal. SYNCLK is ignored if SCLKEN is high. CheckBits-Out (00, 01) Partial-CheckBits-Out (10) Checkbits-Out (11): In a single EDC system, the checkbits are output to the checkbit memory on these outputs. In the lower slice in a cascaded EDC system, the "Partial-checkbits" used by the upper slice are output by these outputs (Generate path only). In the upper slice in a cascade, the "Final-Checkbits" appear at these outputs (Generate path only). CheckBits Out Enable: Enables CheckBit Output drivers when low. SYndrome-Out (00) Partial-SYndrome-Out (10) Partial-Checkbits-Out (11): In a 32-bit EDC system, the syndrome bits are output on these pins. In the lower slice in a 64-bit cascaded system, the "Partial-Syndrome" bits appear at these outputs (Detect/ Correct path). In the upper slice in a cascaded EDC system, the "Partial-Checkbits" appear at these outputs (Correct path only). In a 64-bit cascaded system, the "Final-Syndrome" may be accessed in the "Diagnostic-Output" Mode from either the lower or the upper slice since the final syndrome is contained in both. ERROR: When in "Normal" and "Detect only" modes, a low on this pin indicates that one or more errors have been detected. ERR is not gated or latched internally. Multiple ERRor: When in "Normal" and "Detect only" modes, a low on this pin indicates that two or more errors have been detected. MERR is not gated or latched internally. Parity ERRor: A low on this pin indicates a parity error which has resulted from the active bytes defined by the 4 Byte Enable pins. Parity ERRor (PERR) is not gated or latched internally (see Byte Enable definition). +5 Volts Ground
2552 tbl 02
(x01)
(100)
CLEAR
SYNCLK
I I
SCLKEN
CBO0-7
I
Outputs and Enables O
CBOE
SYO0-7
I O
ERR MERR PERR
Vcc 1- 10 GND1-12
O O O
Power Supply Pins P P
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IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
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DIAGNOSTIC DATA FORMAT (SYSTEM BUS)
Latched Data Error ReType served Error Counter Data Out (Unlatched)
Syndrome bits Byte 2 7 6 5 4 3 2 1 0 7 6
Partial Checkbits Byte 1 5 4 3 2 1 0 7 6
Checkbits Byte 0 5 4 3 2 1 0 0
2552 drw 12
Byte 3 S 31 M 30 23 2 2 21 20 27
24 23
16 15
87
DIAGNOSTIC FEATURES -- DETAILED DESCRIPTION
Mode 2-0 x11 x10 "NORMAL" Mode In this mode, operation is "Normal" or non-diagnostic. "GENERATE-DETECT" Mode When the EDC unit is in the "Generate-Detect" Mode, data is not corrected or altered by the error correction network. (Also referred to as the "Detect-only" Mode.) "ERROR-DATA-OUTPUT" Mode In this mode, the 32-bit data from the Error-Data Register is output on the SD bus. Error Data Register: The uncorrected data from the Memory Data bus input latch is stored in the Error-Data Register if the error counter contents indicates "0" and there is a positive transition on the SYNCLK input when the ERR signal is low. Thus, the Error-Data Register contains memory data corresponding to the first error to occur since the register was cleared. This register is cleared by pulling the CLEAR input low. The register is read via the System Data bus by entering the "Error-Data-Output" Mode and enabling the System Data bus output drivers. All-Zero-Data: The Error-Data Register can be used as an "all-zero-data" data source for memory initialization in systems where the initialization process is to be done entirely by hardware. x01 "DIAGNOSTIC-OUTPUT" Mode In this mode, data from the diagnostic registers, the PCBI bus and the CBI bus is output on the SD bus. Direct Checkbit Readback: Internal data paths allow both the "Partial-CheckBit-Input" bus and the data in the "CheckBitInput" latch to be read directly by the system bus for diagnostic purposes. Both the Checkbit Input Bus and the Partial Checkbit Input Bus are read via the System Data bus by entering the "Diagnostic-Output" Mode and enabling the System Data bus output drivers. The checkbits are output on System Data bus bits 0-7; the Partial Checkbits are output on bits 8-15. Syndrome Register: After an error has been detected, the syndrome bits generated are clocked into the internal Syndrome Register if the error counter contents indicates "0" and there is a positive transition on the SYNCLK input when the ERR signal is low. This register is cleared by pulling the CLEAR input low. The register is read via the System Data bus by entering the "Diagnostic-Output" Mode and enabling the System Data bus outputs. This data is output on SD bits 16-23. Error Counter: The 4-bit on-board error counter is incremented if the error counter contents do not indicate FF HEX, which corresponds to a count of 15, and there is a positive transition on the SYNCLK input when the ERR signal is low. This counter is cleared by pulling the CLEAR input low. The counter is read via the System Data bus by entering the "Diagnostic-Output" Mode and enabling the System Data bus output drivers. This data is output on System Data bus bits 24-27. Test Register: These 2 bits are reserved for factory diagnostics only and must not be used by system software. This data is output on System Data bus bits 28-29. Error-Type Register: The Error-Type Register, clocked by the SYNCLK input, saves 2 bits which indicate whether a recorded error was a single or a multiple-bit error. This register holds only the first error type to occur after the last Clear operation. This data is output on System Data bus bits 30-31. 100 Direct Read-Path Checkbit Injection: In the "Checkbit-Injection" Mode, bits 0-7 of the System Data input latch are presented to the inputs of the Checkbit Input latch. If MLE is strobed, the checkbit latch will be loaded with this value in place of the checkbits from memory. By inserting various checkbit values, operation of the correction function of the EDC can be verified "on-board". Except for the "Checkbit-Injection" function, operation in this mode is identical to "Normal" Mode operation.
2552 tbl 03
000
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IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OPERATING MODE CHARTS SLICE IDENTIFICATION
CODE ID 1 0 0 1 1 CODE ID 0 0 1 0 1 Slice Definition 32-bit Flow-Thru EDC 64-bit GENERATE Only EDC 64-bit EDC- Lower 32 bits (0-31) 64-bit EDC- Upper 32 bits (32-63)
2552 tbl 04
SLICE POSITION CONTROL
Checkbit Buses Slice Position/ CODE Functional Operation ID 10 00 PCBI PCBI Bus 8 -- -- -- -- U-SYOout CBI CBI Bus 8 -- CBs in -- -- CBs in CBO CBO Bus 8 CBs out -- CBs out SYO SYO Bus 8 -- Syn. out -- P P Bus 4
SOE
Width = Single 32-bit EDC unit Generate(1) Detect/Correct(2) "64-bit Generate-only" Lower word, 64-bit bus Generate(1) Detect/Correct(2) Upper word, 64-bit bus Generate(1) Detect/Correct(2) 1 0 1 1 0 1 0
SD Bus 32 Sys. 0-31 Pipe. latch Sys. 32-63 Sys. 0-31 Pipe. latch Sys. 32-63 Pipe. latch
MOE
0 1 1 0 1 0 1
MD Bus 32 Sys. Byte Mux MD 0-31 Sys. 0-31 MD 0-31 MD 0-31 MD 32-63 MD 32-63
PERR
1
P in active P out -- -- --
01 10
PCBs out -- P in active -- Par.Synd P out --
11
L-CBOout -- F.CBs out -- P in active -- L-SYOout -- Par.Cbits P out --
2552 tbl 05
NOTES: 1. Checkbits generated from the data in the SD Latch. 2. Corrected data residing in the Pipe Latch.
FUNCTIONAL MODE CONTROL
Checkbit Buses Functional Mode of SD Bus MODE 210 x11 Width = "Normal" Generate Correct "Generate-Detect" Generate Detect "Error-Data-Output" "Diagnostic-Output" 1 0 1 0 0 0 PCBI CBI Bus 8 -- CB in -- CB in -- CB in CBO Bus 8 CB out -- CB out -- -- -- SYO Bus 8 -- -- -- -- -- -- P Bus 4
SOE
SD Bus 32 CPU Data Pipe. latch CPU Data Pipe. latch Err. D. latch CBin latch PCBIin bus Syn. register Err. counter Er. type reg. SDin latch SD0-7 in Pipe. latch
MOE
0 1 0 1 -- --
MD Bus 32 Pipe. latch RAM Data Pipe. latch RAM Data -- --
Bus 8 -- -- -- -- -- PCBI in
PERR
1
P in active P out -- P in active P out -- -- -- -- --
x10
000 x01
100
"Checkbit-Injection" Generate Inject Checkbits Correct
1 1 0
0 0 1
Pipe. latch Pipe. latch RAM Data
-- -- --
-- -- CB in
CB out -- --
-- -- --
P in active -- -- P out --
2552 tbl 06
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IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PRIMARY DATA PATH vs. MEMORY CONFIGURATION
SEPARATE I/O MEMORIES: COMMON I/O MEMORIES:
1. Checkbit Generation Write New Word to Memory CPU DIN MAIN MEMORY SD MD P CBO IDT49C465 CBI DOUT CHECKBIT MEMORY
1. Checkbit Generation Write New Word to Memory
2. Data Correction Read Memory Word CPU DIN MAIN MEMORY DOUT CHECKBIT MEMORY
3. Memory Generation Re-write Corrected Word to Memory CPU DIN MAIN MEMORY SD MD P CBO IDT49C465 CBI DOUT CHECKBIT MEMORY
BUFFER
IDT49C465
CPU
SD P
MD
I/O MAIN MEMORY CHECKBIT MEMORY
CBO IDT49C465 CBI
2. Data Correction Read Memory Word
BUFFER BUFFER
CORRECTED
CORRECTED SD CPU P
MD
I/O MAIN MEMORY CHECKBIT MEMORY
SD MD P CBO CBI
CBO IDT49C465 CBI
3. Memory Generation Re-write Corrected Word to Memory
CORRECTED
CORRECTED SD CPU P
CORRECTED MD I/O MAIN MEMORY CHECKBIT MEMORY
CBO IDT49C465 CBI
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IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PARTIAL-WORD-WRITE OPERATIONS
FOR COMMON I/O MEMORIES:
MD LATCH
CORRECTION BLOCK
B3
PIPE LATCH
MD BUS
SD BUS BYTE 3 BYTE 2 BYTE 1 BYTE 0
B2 B1 B0 BYTE MUX
BYTE 3 BYTE 2 BYTE 1 BYTE 0 MAIN MEMORY
8
SD LATCH
A3 A2 A1 A0
8 8 8
CHECKBIT GENERATOR CBO
B3 = 1 B2 = 1 B1 = 1 B0 = 0
CBI IDT49C465
CHECKBIT MEMORY
2552 drw 14
In order to perform a partial-word-write operation, the complete word in question must be read from memory. This must be done in order to correct any error which may have occurred in the old word. Once the complete, corrected word is available, with all the bytes verified, the new word may be assembled in the byte mux and the new checkbits generated.
The example shown above illustrates the case of combining 3 bytes from an old word with a new lower order byte to form a new word. The new word, along with the new checkbits, may now be written to memory. In the separate I/O memory configuration, the situation is similar except that the new word is output on the SD Bus instead of the MD Bus (refer to previous page).
11.7
12
IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
32-BIT DATA WORD CONFIGURATION
A single IDT49C465 EDC unit, connected as shown below, provides all the logic needed for single-bit error correction, and double-bit error detection, of a 32-bit data field. The identification code (00) indicates 7 checkbits are required. The CBI7 pin should be tied high. The 39-bit data format for four bytes of data and 7 checkbits is indicated below. Syndrome bits are generated by an exclusive-OR of the generated checkbits with the checkbits read from memory. For example, Sn is the XOR of checkbits from those read with those generated. During Data Correction, the syndrome bits are used to complement (correct) single-bit errors in the data bits.
32-BIT DATA FORMAT
DATA BYTE 3 31 24 23 BYTE 2 16 15 BYTE 1 87 BYTE 0 0 C6 C5 CHECKBITS C4 C3 C2 C1 C0
2552 drw 15
32-BIT HARDWARE CONFIGURATION
VCC 8 PCBI0-7 CBI7 CHECKBITS-IN 7 CBI0-6 SYO0-6 7 SYNDROME-OUT CBO0-6 7 CHECKBITS-OUT
ERR
P0-3 SD0-31
MERR
MD0-31 32 MEMORY DATA I/O
SYSTEM DATA I/O
32
CODE ID 1,0 = 00
IDT49C465
2552 drw 16
11.7
13
IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
64-BIT DATA WORD CONFIGURATION
Two IDT49C465 EDC units, connected as shown below, provide all the logic needed for single-bit error correction, and double-bit error detection, of a 64-bit data field. The "Slice Identification" Table gives the CODE ID1,0 values needed for distinguishing the upper 32 bits from the lower 32 bits. Final generated checkbits, ERR and MERR (indicates multiple errors) signals come from the upper slice, the IC with CODE ID1,0=11. Control signals not shown are connected to both units in parallel. Data-In bits 0 through 31 are connected to the same numbered inputs of the EDC with CODE ID1,0=10, while Data-In bits 32 through 63 are connected to data inputs 0 to 31, respectively, for the EDC unit with CODE ID1,0=11. The 72-bit data format of data and checkbits is indicated below. Correction of single-bit errors in the 64-bit configuration requires a simultaneous exchange of partial checkbits and partial syndrome bits between the upper and lower units. Syndrome bits are generated by an exclusive-OR of the generated checkbits with the checkbits read from memory. For example, Sn is the XOR of checkbits read and checkbits generated. During data correction, the syndrome bits are used to complement (correct) single-bit errors in the data bits. For double or multiple-bit error detection, the data available as output by the Pipeline Latch is not defined. Critical AC performance data is provided in the Table "Key AC Calculations", which illustrates the delays that are critical to 64-bit cascaded performance. As indicated, a summation of propagation delays is required when cascading these units.
64-BIT DATA FORMAT
DATA BYTE 7 BYTE 6 BYTE 5 BYTE 4 BYTE 3 BYTE 2 BYTE 1 BYTE 0 63 56 55 48 47 40 39 32 31 24 23 16 15 87 0 C7 C6 C5 CHECKBITS C4 C3 C2 C1 C0
2552 drw 17
64-BIT HARDWARE CONFIGURATION
8
PARTIAL-CHECKBITS (CORRECT ONLY) PCBI0-7 CBI0-7
PCBI0-7
CHECKBITS-IN
CBO0-7 SYO0-7
8
CBI0-7
8 PARTIAL-CHECKBITS (GENERATE ONLY) 8 PARTIAL-SYNDROME (DETECT/CORRECT)
CBO0-7 SYO0-7 ERR
8 FINAL CHECKBITS (GENERATE ONLY)
(DETECT AND CORRECT) P0-3 MERR MD0-31 MEMORY DATA 32-63
P0-3
SYSTEM DATA 0-31
SD0-31
SD0-31
IDT49C465 LOWER EDC (CODE ID 1,0 = 10) SYSTEM DATA 32-63
IDT49C465 UPPER EDC (CODE ID 1,0 = 11) MEMORY DATA 0-31
2552 drw 18
11.7
14
IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DEFINITIONS OF TERMS:
D0 - D31 CBI0 - CBI7 PCBI0 - PCBI7 FS0 - FS7 = = = = System Data and/or Memory Data Inputs Checkbit Inputs Partial Checkbit Inputs Final Internal Syndrome bits
CMOS TESTING CONSIDERATIONS
Special test board considerations must be taken into account when applying high-speed CMOS products to the automatic test environment. Large output currents are being switched in very short periods and proper testing demands that test set-ups have minimized inductance and guaranteed zero voltage grounds. The techniques listed below will assist the user in obtaining accurate testing results: 1) All input pins should be connected to a voltage potential during testing. If left floating, the device may oscillate, causing improper device operation and possible latchup. 2) Placement and value of decoupling capacitors is critical. Each physical set-up has different electrical characteristics and it is recommended that various decoupling capacitor sizes be experimented with. Capacitors should be positioned using the minimum lead lengths. They should also be distributed to decouple power supply lines and be placed as close as possible to the DUT power pins. 3) Device grounding is extremely critical for proper device testing. The use of multi-layer performance boards with radial decoupling between power and ground planes is necessary. The ground plane must be sustained from the performance board to the DUT interface board and wiring unused interconnect pins to the ground plane is recommended. Heavy gauge stranded wire should be used for power wiring, with twisted pairs being recommended for minimized inductance. 4) To guarantee data sheet compliance, the input thresholds should be tested per input pin in a static environment. To allow for testing and hardware-induced noise, IDT recommends using VIL 0V and VIH 3V for AC tests.
FUNCTIONAL EQUATIONS:
The equations below describe the terms used in the IDT49C465 to determine the values of the partial checkbits, checkbits, partial syndromes and final internal syndromes. NOTE: All "" symbols below represent the "EXCLUSIVEOR" function. PA = D0 D1 D2 D4 D6 D8 D10 D12 D16 D17 D18 D20 D22 D24 D26 D28 PB = D0 D3 D4 D7 D9 D10 D13 D15 D16 D19 D20 D23 D25 D26 D29 D31 PC = D0 D1 D5 D6 D7 D11 D12 D13 D16 D17 D21 D22 D23 D27 D28 D29 PD = D2 D3 D4 D5 D6 D7 D14 D15 D18 D19 D20 D21 D22 D23 D30 D31 PE = D8 D9 D10 D11 D12 D13 D14 D15 D24 D25 D26 D27 D28 D29 D30 D31 PF = D0 D1 D2 D3 D4 D5 D6 D7 D24 D25 D26 D27 D28 D29 D30 D31 PG = D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 PH0 = D0 D4 D6 D7 D8 D9 D11 D14 D17 D18 D19 D21 D26 D28 D29 D31 PH1 = D1 D2 D3 D5 D8 D9 D11 D14 D17 D18 D19 D21 D24 D25 D27 D30 PH2 = D0 D4 D6 D7 D10 D12 D13 D15 D16 D20 D22 D23 D26 D28 D29 D31
11.7
15
IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DETAILED DESCRIPTION -- CHECKBIT AND SYNDROME GENERATION vs. CODE ID
LOGIC EQUATIONS FOR THE CBO OUTPUTS
CODE ID 1,0 Checkbit CBO0 CBO1 CBO2 CBO3 CBO4 CBO5 CBO6 CBO7 00 PH0 PA 10 Partial Checkbits PH1 PA 11 Final Checkbits PH2 PCBI0 PA PCBI1 PB PCBI2 PC PCBI3 PD PCBI4 PE PCBI5 PF PCBI6 PG PCBI7
2552 tbl 07
32-BIT SYNDROME DECODE TO BIT-IN-ERROR (1)
HEX S6 Syndrome Bits HEX 0 1 2 3 4 5 6 7 8 9 S3 S2 S1 S0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * C0 C1 T C2 T T M C3 T T 17 T M 16 T C4 C5 T T 18 T 19 T T T T 8 T 9 T T T 14 M T 15 T T M M T T M T M M T C6 T T M T M M T T M 1 T M T T 0 T M 2 T 3 T T 4 5 T T 6 T 7 M T T M 24 T 25 T T 26 27 T T 28 T 29 M T 30 T T M T 31 M T T M M T M T T M S5 S4 0 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1
Generation Final Chkbits
PB PC
PD PE PF --
PB PC
PD PE PF PF
20 10
LOGIC EQUATIONS FOR THE SYO OUTPUTS
Checkbit/ Syndrome Generation SYO0 SYO1 SYO2 SYO3 SYO4 SYO5 SYO6 SYO7 00 PH0 CBI0 PA CBI1 CODE ID 1,0 10 PH1 CBI0 PA CBI1 11 PH2 PA PB PC PD PE PF PG
2552 tbl 08
21 11 22 12 T T T M T T T M 23 13
A B C D E F
Final Syndrome Partial Syndrome Partial Checkbits
PB CBI2 PC CBI3
PD CBI4 PE CBI5 PF CBI6 --
PB CBI2 PC CBI3
PD CBI4 PE CBI5 PF CBI6 PF CBI7
LOGIC EQUATIONS FOR THE FINAL SYNDROME (FSn)
Final Syndrome Generation FS0 FS1 FS2 FS3 FS4 FS5 FS6 FS7 00 Final Syndrome PH0 CBI0 PA CBI1 CODE ID 1,0 10, 11 Final Internal Syndrome PH1 (L) PH2 (U) CBI0 PA (L) PA (U) CBI1 PB (L) PB (U) CBI2 PC (L) PC (U) CBI3 PD (L) PD (U) CBI4 PE (L) PE (U) CBI5 PF (L) PF (U) CBI6 PF (L) PG (U) CBI7
2552 tbl 09
NOTES: 2552 tbl 12 1. The table indicates the decoding of the seven syndrome bits to identify the bit-in-error for a single-bit error, or whether a double or triple-bit error was detected. The all-zero case indicates no error detected. * = No errors detected # = The number of the single bit-in-error T = Two errors detected M = Three or more errors detected
PB CBI2 PC CBI3
PD CBI4 PE CBI5 PF CBI6 --
11.7
16
IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DETAILED DESCRIPTION -- 32-BIT CONFIGURATION
32-BIT MODIFIED HAMMING CODE -- CHECKBIT ENCODING CHART(1)
Generated Checkbits CB0 CB1 CB2 CB3 CB4 CB5 CB6 Generated Checkbits CB0 CB1 CB2 CB3 CB4 CB5 CB6 Parity Even (XOR) Even (XOR) Odd (XNOR) Odd (XNOR) Even (XOR) Even (XOR) Even (XOR) X X X X X X X 16 17 X X 18 X X X 19 X X X X X X X 20 21 X X X X X X X X X X X X X X X X X X X Parity Even (XOR) Even (XOR) Odd (XNOR) Odd (XNOR) Even (XOR) Even (XOR) Even (XOR) X X X X X X X X
2552 tbl 10
Participating Data Bits 0 X X X X X X X X X X X 1 2 3 4 X X X X X X X 5 6 X X X X X X X X X X X 7 X 8 X X X 9 X X X X X 10 11 X X X X X X X X X 12 13 14 X 15
Participating Data Bits 22 23 24 25 26 X X X X X 27 28 X X X X X X X X X X X 29 X 30 31 X
NOTE: 2552 tbl 11 1. The table indicates the data bits participating in the checkbit generation. For example, checkbit C0 is the Exclusive-OR function of the 16 data input bits marked with an X.
11.7
17
IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DETAILED DESCRIPTION -- 64-BIT CONFIGURATION
Generated Checkbits CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 Generated Checkbits CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 Generated Checkbits CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 Parity Even (XOR) Even (XOR) Odd (XNOR) Odd (XNOR) Even (XOR) Even (XOR) Even (XOR) Even (XOR) X X X X X X 32 X X X X X X X X X X X 33 34 35 36 X X X X X 37 Parity Even (XOR) Even (XOR) Odd (XNOR) Odd (XNOR) Even (XOR) Even (XOR) Even (XOR) Even (XOR) X X X X X X X 16 17 X X 18 X X X 19 X X X X X 20 21 X Parity Even (XOR) Even (XOR) Odd (XNOR) Odd (XNOR) Even (XOR) Even (XOR) Even (XOR) Even (XOR) X X X X X X X X X X X X X X X X X X X 0 1 X X 2 X X X 3 X X X X X 4 5 X
64-BIT MODIFIED HAMMING CODE - CHECKBIT ENCODING CHART(1, 2)
Participating Data Bits 6 X X X X X X X X X X X
2552 tbl 13
7
8 X X
9 X
10 X
11 X
12 X
13
14 X
15
X
X X X X
X X X
X X X
X
X
X
X
X
Participating Data Bits 22 X X X X X X X X X X X X X X X X X X X X X X X X 23 24 X X X 25 X X X X X 26 27 X X X X X X X X X X X X
2552 tbl 14
28
29
30 X
31
X
Participating Data Bits 38 X X X X X X X X X X X X X X X X X X
2552 tbl 15
39 X
40 X
41
42 X X
43
44 X X
45 X X
46
47 X X
X
X X X X
X X X X X X
X
X
X
Generated Checkbits CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 Parity Even (XOR) Even (XOR) Odd (XNOR) Odd (XNOR) Even (XOR) Even (XOR) Even (XOR) Even (XOR) X X X X X X 48 X X X X X X X X X X X 49 50 51 52 X X X X X 53
Participating Data Bits 54 X X X X X X X X X X X X X X X X X X X X X 55 X X X 56 57 58 X X X X X 59 60 X X X X X X X X X X X 61 X 62 63 X
NOTES: 2552 tbl 16 1. The table indicates the data bits participating in the checkbit generation. For example, checkbit C0 is the Exclusive-OR function of the 64 data input bits marked with an X. 2. The checkbit is generated as either an XOR or an XNOR of the 64 data bits noted by an "X" in the table. 11.7 18
IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DETAILED DESCRIPTION -- 64-BIT CONFIGURATION (Con't.)
64-BIT SYNDROME DECODE TO BIT-IN-ERROR(1)
HEX S7 S6 Syndrome Bits HEX 0 1 2 3 4 5 6 7 8 9 A B C D E F S3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 S2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * C0 C1 T C2 T T M C3 T T 17 T M 16 T C4 T T 18 T 19 20 T T 21 22 T 23 T T M C5 T T 8 T 9 10 T T 11 12 T 13 T T M T 14 M T 15 T T M M T T M T M M T C6 T T M T M M T T M 33 T M T T 32 T M 34 T 35 T T 36 37 T T 38 T 39 M T T M 56 T 57 T T 58 59 T T 60 T 61 M T 62 T T M T 63 M T T M M T M T T M C7 T T M T M M T T M 49 T M T T 48 T M 50 T 51 T T 52 53 T T 54 T 55 M T T M 40 T 41 T T 42 43 T T 44 T 45 M T 46 T T M T 47 M T T M M T M T T M T M M T M T T M M T T 1 T M 0 T M T T 2 T 3 4 T T 5 6 T 7 T T M M T T 24 T 25 26 T T 27 28 T 29 T T M T 30 M T 31 T T M M T T M T M M T S5 S4 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 A 1 0 1 0 B 1 0 1 1 C 1 1 0 0 D 1 1 0 1 E 1 1 1 0 F 1 1 1 1
NOTES: 2552 tbl 17 1. The table indicates the decoding of the seven syndrome bits to identify the bit-in-error for a single-bit error, or whether a double or triple-bit error was detected. The all-zero case indicates no error detected. * = No errors detected # = The number of the single bit-in-error T = Two errors detected M = Three or more detected
KEY AC CALCULATIONS -- 64-BIT CASCADED CONFIGURATION
64-Bit Propagation Delay Mode Generate Detect From SD Bus MD Bus MD Bus Correct MD Bus To Checkbits out Total AC Delay for IDT49C465 in 64-bit Mode (L) = Lower slice (U) = Upper slice SD to CBO(L) t SC(L) MD to SYO(L) t MSY(L) MD to SYO(L) t MSY(L) MD to SYO(L) t MSY(L) (or) MD to SYO(U) t MSY(U) + + + + + + + + + + PCBI to CBO(U) t PCC(U) CBI to ERR (U) t CE (U) CBI to M ERR t CME (U) CBI to SD(U) t CS (U) PCBI to SD(L) t PCS(L)
2552 tbl 18
ERR for 64-bits MERR for 64-bits
Corrected data out
NOTE: 1. (or) = Whichever is worse.
11.7
19
IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VCC VTERM Rating Power Supply Voltage Terminal Voltage with Respect to Ground Operating Temperature Temperature Under Bias Storage Temperature DC Output Current Com'l. Mil. Unit V V -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 0 to +70 -0.5 to VCC + 0.5 -55 to +125
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Pkg. PGA PQFP PGA PQFP Typ. 10 5 12 7 Unit pF pF
2552 tbl 20
TA TBIAS TSTG IOUT
C C C mA
NOTE: 1. This parameter is sampled and not 100% tested.
-55 to +125 -65 to +135 -55 to +125 -65 to +150 30 30
NOTE: 2552 tbl 19 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to Absolute Maximum Ratings for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
The following conditions apply unless otherwise specified: Commercial: TA = 0C to +70C, VCC = 5.0V 5%; Military: TA = -55C to +125C, VCC = 5.0V 10%
Symbol VIH VIL IIH IIL IOZ IOS VOH VOL VH Parameter Input HIGH Level
(4)
Test Conditions(1) Guaranteed Logic HIGH Normal Inputs Hysteresis Inputs Guaranteed Logic LOW VCC = Max., VIN = VCC VCC = Max., VIN = GND VCC = Max. VCC = Max. VCC = Min. VIN = VIH or VIL VCC = Min. VIN = VIH or VIL
(3)
Min. 2.0 3.0 -- -- --
Typ.(2) -- -- -- -- -- -- -- -- -- -- -- -- 200
Max. -- -- 0.8 5.0 -5.0 -10 10 -150 -- -- 0.5 0.5 --
Unit V V A A A mA V V mV
2552 tbl 21
Input LOW Level(4) Input HIGH Current Input LOW Current Off State (Hi-Z) Short Circuit Current Output HIGH Voltage Output LOW Voltage Hysteresis
VO = 0V VO = 3V IOH = -6mA IOH = -4mA IOL = 12mA IOL = 6mA COM'L. MIL. COM'L. MIL.
-- -- -20 2.4 2.4 -- -- --
CLEAR, MLE, PLE, SLE, SYNCLK, SCLKEN
NOTES: 1. For conditions shown as min. or max., use appropriate value specified above for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient temperature and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. 4. These input levels provide zero noise immunity and should only be static tested in a noise-free environment.
11.7
20
IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Con't.)
The following conditions apply unless otherwise specified: Commercial: TA = 0C to +70C, VCC = 5.0V 5%; Military: TA = -55C to +125C, VCC = 5.0V 10%
Symbol ICCQ Parameter Quiescent Power Supply Current CMOS Input Levels Quiescent Power Supply Current TTL Input Levels Dynamic Power Supply Current f = 10MHz Dynamic Power Supply Current f = 20MHz Test Conditions(1) VIN = VCC or GND VCC = Max. All Inputs Outputs Disabled VIH = 3.4V, VIL = 0V VCC = Max. All Inputs Outputs Disabled fCP = 10MHz, 50% Duty Cycle VIH = VCC, VIL = GND Read Mode, Outputs Disabled fCP = 20MHz, 50% Duty Cycle VIH = VCC, VIL = GND Read Mode, Outputs Disabled COM'L. MIL. COM'L. MIL. Min. -- Typ.(2) -- Max. 5 Unit mA
ICCQT
--
--
1
mA/ input mA
ICCD1
-- -- -- --
-- -- -- --
100 115 200 230
ICCD2
mA
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified above for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient temperature, and maximum loading. 3. Total supply current is the sum of the Quiescent current and the dynamic current and is calculated as follows: ICC = ICCQ + ICCQT (NT x DT) + ICCD (fOP) where: NT = Total # of quiescent TTL inputs DT = AC Duty cycle - % of time high (TTL) fOP = Operating frequency
2552 tbl 22
11.7
21
IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC PARAMETERS - 49C465A
PROPAGATION DELAY TIMES
32-bit System Standalone Slice
CODE ID=00
64-bit "Generate only" Slice
64-bit System Lower Slice Upper Slice Refer to Timing Diagram Figure
CODE ID=01 CODE ID=10 CODE ID=11
Parameter Description Com. Mil. Com. Mil. Com. Mil. Com. Mil. Number Parameter From To Name Input (edge) Output (edge) Max. Max. Max. Max. Max. Max. Max. Max. Unit
GENERATE (WRITE) PARAMETERS
01 02 03 04 05 06 07 08 t BC t BM t MC t PCC t PPE t SC t SM tSPE SDIN BEN BEN MDIN PCBI PXIN CBO MDOUT CBO CBO 15 15 -- -- 12 14 12 12 20 20 -- -- 18 18 18 18 -- -- 15 -- -- 14 -- -- -- -- 18 -- -- 18 -- -- 15 15 -- -- 12 14 12 12 20 20 -- -- 18 18 18 18 15 15 -- 12 12 14 12 12 20 20 -- 18 18 18 18 18 ns ns ns ns ns ns ns ns -- -- 10 7 -- 7 7 --
PERR
CBO MDOUT
PERR ERR Low MERR = Low
SYO MDIN
DETECT (READ) PARAMETERS
09 10 11 12 13 14 t CE t CME t CSY t ME t MME t MSY CBI 14 15 12 12 16 16 18 20 18 18 20 20 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 12 -- -- 12 -- -- 18 -- -- 18 12 15 -- 12 16 12 18 20 -- 18 20 18 ns ns ns ns ns ns 8,10 8,10 8,10 8,10 8,10 8,10
ERR MERR
SYO
CORRECT (READ) PARAMETERS
15 16 17 18 19 t CS t MP t MS t MSY t PCS PCBI MDIN CBI SDOUT Px SDOUT SYO SDOUT 16 18 14 16 -- 20 22 18 20 -- -- -- -- -- -- -- -- -- -- -- -- 18 -- 12 13 -- 22 -- 18 18 16 18 -- 12 -- 20 22 -- 18 -- ns ns ns ns ns 8,11 8,11 8,11 8,11 11
DIAGNOSTIC PARAMETERS
20 21 t CLR t MIS CLEAR = Low SDOUT MODE ID SDOUT 15 15 20 20 -- -- -- -- 15 15 20 20 15 15 20 20 ns ns 15 15
2552 tbl 24
NOTES: 1. Where "edge" is not specified, both HIGH and LOW edges are implied. 2. BOLD indicates critical system parameters.
11.7
22
IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC PARAMETERS - 49C465A
PROPAGATION DELAY TIMES FROM LATCH ENABLES
Parameter Description Number 22 23 24 25 26 27 28 29 30 31
NOTE:
Com.'l. (edge) * * * * * * * * * * Max. 16 13 16 18 18 15 10 13 16 12
Mil. Max. 20 18 20 22 22 20 12 18 20 18 Unit ns ns ns ns ns ns ns ns ns ns
Refer to Timing Diagram Figure 13 8, 10, 11 8 8, 11 8, 10, 11 8, 10 8, 11 8, 11 7, 9 7, 9
2552 tbl 27
Parameter Name t MLC t MLE t MLME t MLP t MLS t MLSY t PLS t PLP t SLC t SLM
From Input
(edge)
To Output
MLE =
HIGH
ERR MERR
Px SDOUT SYO
CBO
PLE = PLE =
SLE = SLE =
LOW LOW HIGH HIGH
SDOUT Px CBO MDOUT
"*" = Both HIGH and LOW edges are implied. ENABLE AND DISABLE TIMES
Parameter Description Number 32 33 34 35 36 37 38 39 40 41 Parameter Name t BESZx t BESxZ t BEPZx t BEPxZ t CECZx t CECxZ t MEMZx t MEMxZ t SESZx t SESxZ From Input BEN = BEN = (edge) HIGH LOW HIGH LOW LOW HIGH LOW HIGH LOW HIGH To Output (edge) SDOUT POUT CBO MDOUT SDOUT * Hi - Z * Hi - Z * Hi - Z * Hi - Z * Hi - Z Com'l. Min. 2 2 2 2 2 2 2 2 2 2 Max. 13 11 13 11 13 11 13 11 13 11 Min. 2 2 2 2 2 2 2 2 2 2 Mil. Max. 16 14 16 14 16 14 16 14 16 14 Unit ns ns ns ns ns ns ns ns ns ns Refer to Timing Diagram Figure 8, 10, 11 8, 11 7, 9 7, 9 8, 10 8, 10 7, 9
2552 tbl 28
CBOE = MOE = SOE =
NOTE: "*" = Delay to both edges.
11.7
23
IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SET-UP AND HOLD TIMES - 49C465A
Parameter Description Number 42 43 44 45 46 47 48 49 50 51 52 53 Parameter Name t SSLS t SSLH t MMLS t MMLH t CMLS t CMLH t MPLS t MPLH t CPLS t CPLH t PCPLS t PCPLH From Input (edge) * * * * * * * * * * * * To Output (edge) Com.'l. Min. 3 3 3 3 3 3 10 0 10 0 10 0 Mil. Min. 4 4 4 4 4 4 12 0 12 0 12 0 Unit ns ns ns ns ns ns ns ns ns ns ns ns Refer to Timing Diagram Figure 7, 9 7, 9 8, 10, 11 8, 10, 11 8, 10, 11 8, 10, 11 -- -- -- -- -- --
SDIN Set-up SDIN Hold MDIN Set-up MDIN Hold CBI Set-up CBI Hold MDIN Set-up MDIN Hold CBI Set-up CBI Hold PCBI Set-up PCBI Hold
before SLE = LOW after SLE = LOW before MLE =LOW after MLE = LOW before MLE = LOW after MLE = LOW before PLE = HIGH after PLE = HIGH before PLE =HIGH after PLE = HIGH before PLE = HIGH after PLE = HIGH
DIAGNOSTIC SET-UP AND HOLD TIMES
54 55 56 57 58 t CSCS t MSCS t MLSCS t SESCS t SESCH CBI Set-up * MDIN Set-up * before SYNCLK=HIGH MLE Set-up =HIGH SCLKEN Set-up =LOW SCLKEN Hold =LOW after SYNCLK =HIGH 10 10 10 3 3 12 12 12 4 4 ns ns ns ns ns 15 15 15 15 15
2552 tbl 32
NOTE: "*" = Where "edge" is not specified, both HIGH and LOW edges are implied.
MINIMUM PULSE WIDTH
Refer to Parameter Number 59 60 61 62 63 Name t CLEAR t MLE t PLE t SLE t SYNCLK Minimum Pulse Width Input Min. CLEAR LOW time Min. MLE HIGH time Min. PLE LOW time Min. SLE HIGH time Min. SYNCLK HIGH time to clear diag. registers to strobe new data to strobe new data to strobe new data to clock in new data Conditions Data = Valid MD, CBI = Valid SD = Valid SD = Valid SCKEN = LOW Com'l. Min. 8 5 5 5 5 Mil. Min. 10 6 6 6 6 Unit ns ns ns ns ns Timing Diagram Figure 14 -- -- -- 14
2552 tbl 33
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load
GND to 3.0V 1V/ns 1.5V 1.5V See Figure 18
2552 tbl 34
11.7
24
IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC PARAMETERS - 49C465
PROPAGATION DELAY TIMES
32-bit System Standalone Slice
CODE ID=00
64-bit "Generate only" Slice
64-bit System Lower Slice Upper Slice Refer to Timing Diagram Figure
CODE ID=01 CODE ID=10 CODE ID=11
Parameter Description Com. Mil. Com. Mil. Com. Mil. Com. Mil. Number Parameter From To Name Input (edge) Output (edge) Max. Max. Max. Max. Max. Max. Max. Max. Unit
GENERATE (WRITE) PARAMETERS
01 02 03 04 05 06 07 08 t BC t BM t MC t PCC t PPE t SC t SM tSPE SDIN BEN BEN MDIN PCBI PXIN CBO MDOUT CBO CBO 20 20 -- -- 15 16 15 15 25 25 -- -- 20 20 20 20 -- -- 17 -- -- 16 -- -- -- -- 20 -- -- 20 -- -- 20 20 -- -- 15 16 15 15 25 25 -- -- 20 20 20 20 20 20 -- 15 15 16 15 15 25 25 -- 20 20 20 20 20 ns ns ns ns ns ns ns ns -- -- 10 7 -- 7 7 --
PERR
CBO MDOUT
PERR ERR = LOW MERR = LOW
SYO MDIN
DETECT (READ) PARAMETERS
09 10 11 12 13 14 t CE t CME t CSY t ME t MME t MSY CBI 16 20 15 15 20 18 20 24 20 20 24 22 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 12 -- -- 15 -- -- 18 -- -- 20 15 20 -- 15 20 15 20 24 -- 20 24 20 ns ns ns ns ns ns 8,10 8,10 8,10 8,10 8,10 8,10
ERR = LOW MERR = LOW
SYO
CORRECT (READ) PARAMETERS
15 16 17 18 19 t CS t MP t MS t MSY t PCS PCBI MDIN CBI SDOUT Px SDOUT SYO SDOUT 20 20 16 18 -- 24 26 20 22 -- -- -- -- -- -- -- -- -- -- -- -- 20 -- 15 15 -- 26 -- 20 20 20 20 -- 15 -- 24 26 -- 20 -- ns ns ns ns ns 8,11 8,11 8,11 8,11 11
DIAGNOSTIC PARAMETERS
20 21 t CLR t MIS CLEAR = LOW MODE ID SDOUT SDOUT 20 20 24 24 -- -- -- -- 20 20 24 24 20 20 24 24 ns ns 15 15
2552 tbl 23
NOTES: 1. Where "edge" is not specified, both HIGH and LOW edges are implied. 2. BOLD indicates critical system parameters.
11.7
25
IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC PARAMETERS - 49C465
PROPAGATION DELAY TIMES FROM LATCH ENABLES
Parameter Description Number 22 23 24 25 26 27 28 29 30 31
NOTE:
Com.'l. Max. 20 15 20 20 20 18 12 16 20 15
Mil. Max. 24 20 24 25 25 22 16 20 24 20 Unit ns ns ns ns ns ns ns ns ns ns
Refer to Timing Diagram Figure 13 8, 10, 11 8 8, 11 8, 10, 11 8, 10 8, 11 8, 11 7, 9 7, 9
2552 tbl 25
Parameter Name t MLC t MLE t MLME t MLP t MLS t MLSY t PLS t PLP t SLC t SLM
From Input (edge)
To Output (edge) CBO
MLE = HIGH
ERR MERR
Px SDOUT SYO
* * * * * * * * * *
PLE = PLE =
LOW LOW
SDOUT Px CBO MDOUT
SLE = HIGH SLE = HIGH
"*" = Both HIGH and LOW edges are implied. ENABLE AND DISABLE TIMES
Parameter Description Parameter Number Name 32 33 34 35 36 37 38 39 40 41 t BESZx t BESxZ t BEPZx t BEPxZ t CECZx t CECxZ t MEMZx t MEMxZ t SESZx t SESxZ From Input BEN = BEN = (edge) HIGH LOW HIGH LOW LOW HIGH LOW HIGH LOW HIGH To Output SDOUT POUT CBO MDOUT SDOUT (edge) * Hi - Z * Hi - Z * Hi - Z * Hi - Z * Hi - Z Com'l. Min. 2 2 2 2 2 2 2 2 2 2 Max. 15 13 15 13 15 13 15 13 15 13 Min. 2 2 2 2 2 2 2 2 2 2 Mil. Max. 18 16 18 16 18 16 18 16 18 16 Unit ns ns ns ns ns ns ns ns ns ns Refer to Timing Diagram Figure 8, 10, 11 8, 11 7, 9 7, 9 8, 10 8, 10 7, 9
2552 tbl 26
CBOE = MOE = SOE =
NOTE: "*" = Delay to both edges.
11.7
26
IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SET-UP AND HOLD TIMES - 49C465
Parameter Description Number 42 43 44 45 46 47 48 49 50 51 52 53 Parameter Name t SSLS t SSLH t MMLS t MMLH t CMLS t CMLH t MPLS t MPLH t CPLS t CPLH t PCPLS t PCPLH From Input SDIN Set-up SDIN Hold MDIN Set-up MDIN Hold CBI Set-up CBI Hold MDIN Set-up MDIN Hold CBI Set-up CBI Hold PCBI Set-up PCBI Hold To (edge) Output * * * * * * * * * * * * (edge) Com.'l. Min. 4 4 4 4 4 4 12 0 12 0 12 0 Mil. Min. 5 5 5 5 5 5 15 0 15 0 15 0 Unit ns ns ns ns ns ns ns ns ns ns ns ns Refer to Timing Diagram Figure 7, 9 7, 9 8, 10, 11 8, 10, 11 8, 10, 11 8, 10, 11 -- -- -- -- -- --
before SLE =LOW after SLE = LOW before MLE =LOW after MLE = LOW before MLE =LOW after MLE = LOW before PLE =HIGH after PLE = HIGH before PLE =HIGH after PLE = HIGH before PLE =HIGH after PLE = HIGH
DIAGNOSTIC SET-UP AND HOLD TIMES
54 55 56 57 58 t CSCS t MSCS t MLSCS t SESCS t SESCH CBI Set-up * MDIN Set-up * before SYNCLK=HIGH MLE Set-up = HIGH SCLKEN Set-up = LOW SCLKEN Hold = LOW after SYNCLK =HIGH 12 12 12 4 4 15 15 15 5 5 ns ns ns ns ns 15 15 15 15 15
2552 tbl 29
NOTE: "*" = Where "edge" is not specified, both HIGH and LOW edges are implied.
MINIMUM PULSE WIDTH
Refer to Parameter Number 59 60 61 62 63 Name t CLEAR t MLE t PLE t SLE t SYNCLK Minimum Pulse Width Input Min. CLEAR LOW time to clear diag. registers Min. MLE HIGH time to strobe new data Min. PLE LOW time to strobe new data Min. SLE HIGH time to strobe new data Min. SYNCLK HIGH time to clock in new data Conditions Data = Valid MD, CBI = Valid SD = Valid SD = Valid SCLKEN = LOW Com'l. Min. 8 5 5 5 5 Mil. Min. 10 6 6 6 6 Unit ns ns ns ns ns Timing Diagram Figure 14 -- -- -- 14
2552 tbl 30
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load
GND to 3.0V 1V/ns 1.5V 1.5V See Figure 18
2552 tbl 31
11.7
27
IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TIMING DIAGRAMS -- 32-BIT CONFIGURATION
to BEN
t BESxZ t BESxZ t BESxZ min. t BESxZ max.
1
2
3
4
5
Parameter Name
Propagation Delay From To
Min./ Max.
BEN = Low to SDOUT Disabled BEN = Low to SDOUT Disabled
min. max.
SOE
t SESxZ t SESxZ t SESxZ min. t SESxZ max.
SOE = Low to SDOUT Disabled SOE = Low to SDOUT Disabled
min. max.
SD0-31
(OUTPUT)
DATAIN
t SSLS t SSLH t SSLH t SSLS
SDIN Set-up to SLEIN = Low SDIN Hold to SLEIN = Low
min. min.
SLE
t SPE t SPE
SDIN to PERROUT
max.
PN
t PPE t PPE
Px to PERROUT
max.
PERR
t SM (1) t SLM t SM t SLM
(1)
SDIN to MDOUT SLE = High to MDOUT
max. max.
MOE
tMEMZx t MEMZx
MOE = Low to MDOUT Enabled
max.
MD0-31
(INPUT)
t SC t SLC (1)
M DATAOUT = S DATAIN
t SC t SLC (1)
SDIN to CBO SLE = High to CBO
max. max.
CBOE
t CECZx t CECZx
CBOE = Low to CBO Enable max.
CBO
to
1
2
3
4
5
2552 drw 19
NOTE: 1. Assumes that System Data is valid at least 3ns (Com.) before SLE goes HIGH. Figure 7. 32-Bit Generate Timing
11.7
28
IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TIMING DIAGRAMS -- 32-BIT CONFIGURATION
to 1 2 3 4 5 Parameter Name Propagation Delay From To Min./ Max.
MOE
t MEMxZ t MEMxZ
MOE = High to MDOUT Disabled
max.
MD 0-31
(OUTPUT)
Valid DATAIN
t MMLS t MMLH t MMLS t MMLH
MDIN Set-up to MLE = Low MDIN Hold to MLE = Low
min. min.
CBI
Valid Checkbits In t CMLS t CMLH t CMLH t CMLS
Checkbit Set-up to MLE = Low Checkbit Hold to MLE = Low
min. min.
MLE
t MSY t CSY t MLSY (1) t MSY t CSY t MLSY (1)
MDIN to SYOOUT Checkbits in to SYOOUT MLE = High to SYOOUT
max. max. max.
SYO
t ME t CE t MLEx (1) t ME t CE t MLEx(1)
MDIN to ERR = Low Checkbits in to ERR = Low MLE = High to ERR = Low(1)
max. max. max.
ERR
t MME t CME t MLMEx (1) t MME t CME (1) t MLEMx
MDIN to MERR = Low Checkbits in to MERR = Low MLE = High to MERR = Low (1)
max. max. max.
MERR
to
1
2
3
4
5
2552 drw 20
NOTE: 1. Assumes that Memory Data and Checkbits are valid at least 3ns (Com.)/4ns (Mil,) before MLE goes HIGH. Figure 8. 32-Bit Detect Timing
11.7
29
IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TIMING DIAGRAMS -- 32-BIT CONFIGURATION
to 1 2 3 4 5 Parameter Name Propagation Delay From To Min./ Max.
MOE
t MEMxZ t MEMxZ
MOE = High to MDOUT Disabled
max.
MD 0-31
(OUTPUT)
Valid DATAIN
t MMLS t MMLH t MMLH t MMLS
MDIN Set-up to MLE = Low MDIN Hold to MLE = Low
min. min.
CBI
Valid Checkbits In t CMLS t CMLH t CMLS t CMLH
Checkbit Set-up to MLE = Low Checkbit Hold to MLE = Low
min. min.
MLE
t MLS (1) t MLS (1)
MLEIN = High to SDOUT
(1)
max.
PLE
t PLS (1) t PLS(1)
PLE = Low to SDOUT
(1)
max.
BEN
t BESZx t BESZx
BEN = High to SDOUT Enabled
max.
SOE
t SESZx t CS t MS t SESZx t CS t MS
SOE = Low to SDOUT Enabled CBI to Corrected SDOUT MDIN to Corrected SDOUT
max. max. max.
Corrected DATAOUT
t MP t MLP t PLP t BEPZx t SEP t MP t MLP t PLP t BEPZx t SEP Parity Out
MDIN to Parity Out MLE = High to Parity Out PLE = Low to Parity Out BEN = High to Parity Out SOE = Low to Parity Out
max. max. max. max. max.
P0-3
to
1
2
3
4
5
2552 drw 21
NOTE: 1. Assumes that Memory Data and Checkbits are valid at least 3ns (Com.)/4ns (Mil.) before MLE goes HIGH. Figure 9. 32-Bit Correct Timing
11.7
30
IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TIMING DIAGRAMS -- 64-BIT CONFIGURATION
BOTH 465s
to
1
2
3
4
5 Parameter Name
Propagation Delay From To
Min./ Max.
BEN
SOE
t SESxZ t SESxZ t SESxZ min. t SESxZ max.
SOE = High to SDOUT Disabled SOE = High to SDOUT Disabled
min. max.
SD (L & U)
(OUTPUT)
DATAIN
t SSLS t SSLH t SSLH t SSLS
SDIN Set-up to SLEIN = Low SDIN Hold to SLEIN = Low
min. min.
SLE Px Parity In
t PPE t PPE
Px to PERR
max.
PERR
t SM t SM
SDIN to MDOUT
max.
MOE
t SLM (1) t SLM (1) t MEMZx t BEM t MEMZx t BEM
SLE = High to MDOUT MOE = Low to MDOUT Enabled BEN to MDOUT
max. max. max.
MD (L & U)
(INPUT)
t SC t SLC (1)
MD DATAOUT = SD DATAIN
t SC t SLC (1)
SD Lower In to CBO (1) SLEIN = High to CBO
max. max.
CBOE
t CECZx t CECZx
CBOE = Low to CBO Enabled
max.
LOWER 465 CBO Partial Checkbits Out 3 UPPER 465 PCBI Partial Checkbits In
t PCC t PCC
Inter-chip delay (Design dependent)
PCBI to CBO
max.
CBO
Final Checkbits Out
to
1
2
3
4
5
2552 drw 22
NOTE: 1. Assumes that System Data is valid at least 3ns (Com.)/4ns (Mil.) before SLE goes HIGH. Figure 10. 64-Bit Generate Timing -- (64-Bit Cascading System)
11.7
31
IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TIMING DIAGRAMS -- 64-BIT CONFIGURATION
BOTH 465s
to
1
2
3
4
5
Parameter Name
Propagation Delay From To
Min./ Max.
MOE
t MEMxZ t MEMxZ
MOE = High to MDOUT Disabled MDIN Set-up to MLE = Low MDIN Hold to MLE = Low
max.
MD (L)
(OUTPUT)
Valid DATAIN
t MMLS t MMLH t MMLS t MMLH min. min.
CBI
Valid Checkbits In t CMLS t CMLH t CMLS t CMLH
CBI Set-up to MLE = Low CBI Hold to MLE = Low
min. min.
MLE
t MLS (1) t MLS(1)
MLE = High to SDOUT
(1)
max.
BEN
t BESZx t BESZx
BEN = High to SDOUT Enabled
max.
SOE
t SESZx t SESZx
SOE = Low to SDOUT Enabled
max.
LOWER 465 SD0-31
t MSY t CSY t MLSY
Corrected DATAOUT
t MSY t CSY t MLSY
MD Lower In to SYOOUT CBI to SYO MLE = High to SYO
max. max. max.
SYO UPPER 465 CBI 3
Partial Syndrome Out Inter-chip delay (Design dependent) Partial Syndrome In
t CME t MLME (1) t CME t MLME (1)
CBI to MERR MLE = High to MERR
max. max.
MERR
t CE t MLE (1) t CE t MLE (1)
CBI to ERR MLE = High to ERR
max. max.
ERR
t ME t MME t ME t MME
MDIN to ERR MDIN to MERR
max. max.
MD (U)
(OUTPUT)
Valid DATAIN
to
1
2
3
4
5
2552 drw 23
NOTE: 1. Assumes that System Data is valid at least 3ns (Com.)/4ns (Mil.) before SLE goes HIGH. Figure 11. 64-Bit Detect Timing
11.7
32
IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TIMING DIAGRAMS -- 64-BIT CONFIGURATION
64-BIT U/L Slice
to
1
2
3
4
5
Parameter Name
Propagation Delay From To
Min./ Max.
MOE
t MEMxZ t MEMxZ
MOE = High to MDOUT Disabled
max.
MD 0-31
(OUTPUT)
Valid DATAIN
t MMLS t MMLH t MMLS t MMLH
MDIN Set-up to MLE = Low MDIN Hold to MLE = Low
min. min.
CBI
Valid Checkbits In t CMLS t CMLH t CMLS t CMLH
CBI Set-up to MLE = Low CBI Hold to MLE = Low
min. min.
MLE
(1) t MLS t MLS (1) Partial checkbits in from Upper
MLEIN = High to SDOUT (1)
max.
PCBI
PLE
t PLS (1) t PLS (1) (1)
PLE = Low to SDOUT
max.
BEN
t BESZx t BESZx
BEN = High to SDOUT Enabled
max.
SOE
t SESZx t CS t CSY t MS t SESZx t CS t CSY t MS
SOE = Low to SDOUT Enabled CBI to Corrected SDOUT CBI to Syndrome MDIN to Corrected SDOUT
max. max. max. max.
SD0-31
t CSY t MSY t MP t MLP t PLP t BEPZx t SEP
Corrected DATAOUT
t CSY t MSY t MP t MLP t PLP t BEPZx t SEP
CBI to Syndrome MDIN to Syndrome MDIN to Parity Out MLE = High to Parity Out PLE = Low to Parity Out BEN = High to Parity Out SOE = Low to Parity Out
max. max. max. max. max. max. max.
P0-3
Parity Out
SYO
Partial Syndrome Out
to
1
2
3
4
5
2552 drw 24
NOTE: 1. Assumes that Memory Data and Checkbits are valid at least 4ns (Com.) before MLE goes HIGH. Figure 12. 64-Bit Correct Timing (Lower Slice)
11.7
33
IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TIMING DIAGRAMS -- 64-BIT CONFIGURATION
64-BIT U/L Slice
to
1
2
3
4
5
Parameter Name
Propagation Delay From To
Min./ Max.
MOE
t MEMxZ t MEMxZ
MOE = High to MDOUT Disabled MDIN Set-up to MLE = Low MDIN Hold to MLE = Low
max.
MD 0-31
(OUTPUT)
Valid DATAIN
t MMLS t MMLH t MMLS t MMLH min. min.
CBI
Valid Checkbits In
t CMLS t CMLH
t CMLS t CMLH
CBI Set-up to MLE = Low CBI Hold to MLE = Low
min. min.
MLE
t MLS (1) (1) t MLS
MLEIN = High to SDOUT
(1)
max.
PLE
t PLS (1) t PLS(1)
PLE = Low to SDOUT
(1)
max.
BEN
t BESZx t BESZx
BEN = High to SDOUT Enabled
max.
SOE
t SESZx t CS t MS t MSY t SESZx t CS t MS t MSY
SOE = Low to SDOUT Enabled CBI to Corrected SDOUT MDIN to Corrected SDOUT MDIN to Corrected SDOUT
max. max. max. max.
SD0-31
t MP t MLP t PLP t BEPZx t SEP
Corrected DATAOUT
t MP t MLP t PLP t BEPZx t SEP
MDIN to Parity Out
MLE = High to Parity Out
max. max. max. max. max.
PLE = Low to Parity Out BEN = High to Parity Out SOE = Low to Parity Out
P0-3
Parity Out
SYO to 1 2
Partial Checkbits/ Syndrome Out
3
4
5
2552 drw 25
NOTE: 1. Assumes that Memory Data and Checkbits are valid at least 4ns (Com.) before MLE goes HIGH. Figure 13. 64-Bit Correct Timing (Upper Slice)
11.7
34
IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TIMING DIAGRAMS -- 64-BIT CONFIGURATION
SINGLE 465
to
1
2
3
4
5
Parameter Name
Propagation Delay From To
Min./ Max.
SOE
(SOE = Tied high)
SD Bus
Valid DATAIN
t SSLS t SSLH t SSLS t SSLH
SDIN Set-up to SLEIN = Low SDIN Hold to SLEIN = Low
min. min.
SLE
(1) t SLC t SLC(1)
SLE = High to CBO
(1)
max.
MOE
(MOE = Tied high)
MD Bus
Valid DATAIN
t MMLS t MMLH t MMLS t MMLH
MDIN Set-up to MLEIN = Low MDIN Hold to MLEIN = Low
min. min.
MLE
t SC t MC t MLC (2) t SC t MC t MLC(2)
Bits 32-63 to CBO Bits 0-31 to CBO (2) MLEIN = High to CBO
max. max. max.
CBOE
t CECZx t CECZx
CBOE = Low to CBO Enabled
max.
CBO
Final Checkbits Out
to
1
2
3
4
5
2552 drw 26
NOTE: 1. Assumes that System Data is valid at least 3ns (Com.) before SLE goes HIGH. 2. Assumes that Memory Data is valid at least 4ns (Com.) before MLE goes HIGH. Figure 14. 64-Bit Single Chip "Generate Only" Timing
11.7
35
IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TIMING DIAGRAMS -- DIAGNOSTIC TIMING
to 1 2 3 4 5 Parameter Name Propagation Delay From To Min./ Max.
465
CBI
Checkbits In
t CSCS t CSCS
CBI Set-up to SYNCLK = High
MD Bus
Memory DataIN
t MSCS t MSCS
MDIN Set-up to SYNCLK = High
min.
MLE
t MLSCS t MLSCS
MLE = High Set-up to SYNCLK = High
min.
SCLKEN
t SESCS t SESCH t SESCS t SESCH
SCLKEN Set-up to SYNCLK = High SCLKEN = Hold After SYNCLK = High
min. min.
SYNCLK
t SYNCLK t SCS t CLEAR t SYNCLK t SCS t CLEAR
SCLKEN Pulse Width SCLKEN = High to SDOUT CLEAR Pulse Width
min. max. min.
CLEAR
t CLR t CLR
CLEAR = Low to SDOUT
max.
SD Bus
Valid DataOUT
to
1
2
3
4
5
2552 drw 27
Figure 15. 32-Bit Diagnostic Timing
11.7
36
IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS
V CC 500 VIN Pulse Generator RT D.U.T. 50pF CL
2552 drw 30
SWITCH POSITION
Test
7.0V
Switch
Open Drain Disable Low Enable Low All Other Tests
Closed
VOUT
Open
500
2552 tbl 35 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tSU
tH
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
2552 drw 31
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
1.5V
tREM
1.5V
2552 drw 32
tSU
tH
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE DISABLE 3V CONTROL INPUT tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED tPZH SWITCH OPEN 1.5V 0V 3.5V 1.5V tPHZ 0.3V VOH 0V
2552 drw 34
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V
2552 drw 33
tPLZ
1.5V 0V 3.5V 0.3V VOL
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns
11.7
37
IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
49C465 Device Type
XX Speed
XX Package
X Process/ Temperature Range
BLANK B PQF G BLANK A 49C465
Commercial (0C to +70C) Military (-55C to +125C) Plastic Quad Flatpack Pin Grid Array Standard Speed High Speed 32-Bit Flow-thruTM EDC
2552 drw 35
11.7
38

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